Chip Architectures Becoming More Complex with Chiplets

Figure 1: Visual representation of the BeyondTrust vulnerability chain

The semiconductor industry is undergoing a fundamental architectural shift as chip designers move away from monolithic system-on-chip (SoC) designs toward chiplet-based architectures. According to Semiconductor Engineering, the migration is creating "a confusing array of options and tradeoffs for design teams working at the leading edge."

Chiplets are integrated circuit blocks specifically designed to work together to form larger, more complex chips. Rather than fabricating a single large die, manufacturers are disaggregating systems into smaller functional blocks that can be assembled in advanced packages. The approach addresses two critical challenges: the physical limits of chip scaling and the escalating costs of leading-edge manufacturing.

The economic case for chiplets has become compelling. Data presented by AMD CEO Dr. Lisa Su at IEDM 2017 showed that the cost per yielded square millimeter at 7nm is nearly four times higher than at 45nm. For a 360 mm² monolithic die, yield rates hover around 15 percent. Breaking that same design into four chiplets of approximately 99 mm² each more than doubles the yield to 37 percent, according to WikiChip analysis.

Design teams at companies including Synopsys, Cadence, Arteris, and Keysight Technologies are grappling with new challenges in signal integrity, power distribution, and thermal management. The complexity extends beyond silicon to packaging, where different applications require different solutions. Automotive chiplets may cost as little as $20 per package, while data center packages can reach $2,000, according to Fraunhofer IIS EAS.

On January 30, 2025, Semiconductor Engineering published an extensive analysis of the chiplet transition, featuring insights from multiple EDA vendors and semiconductor experts. The report, authored by Ed Sperling and Ann Mutschler, documented the growing complexity facing chip architects as the industry moves toward disaggregated designs.

The analysis came amid ongoing discussions at the Chiplet Summit, where industry experts gathered to address the technical challenges of multi-die integration. Rajat Chaudhry, product management group director for Voltus at Cadence, described the shift in design methodology: "In the older design style of SoCs, you knew you had a package you could start designing with, assuming you were going to get a certain clean supply at the power pins of your design. Now you have multiple chiplets, and you have to set up that early model for the whole system."

The report identified several driving factors behind the chiplet transition. Wires and SRAM are no longer scaling fast enough to accommodate additional features on a single chip. Breaking complex chips into smaller pieces allows for greater customization, particularly for domain-specific applications. The potential for lower costs and faster time to market exists, especially if a plug-and-play chiplet marketplace becomes viable.

Figure 2: How the authentication bypass vulnerability works

Yield Improvements: According to WikiChip, a 360 mm² monolithic die fabricated with a defect density of 0.1 defects per cm² achieves approximately 15 percent yield. The same design split into four chiplets of 99 mm² each achieves 37 percent yield, even accounting for a 10 percent area overhead for cross-die communication.

Cost Escalation: AMD's data from IEDM 2017 showed that the 16nm process more than doubles the cost per yielded mm² compared to 45nm. The 7nm process nearly quadruples that cost. Costs at 5nm and 3nm are expected to continue increasing.

Signal Integrity Challenges: Chun-Ting "Tim" Wang Lee, signal integrity application scientist at Keysight Technologies, stated: "In chiplets, because all the die are broken up, we have a lot of different die-to-die connections, which means that signal integrity becomes very important. Then, of course, when you have different die, you have power that's going to be on a different die. How are you going to distribute the power to all these other die?"

Timing Complexity: Lee Vick, vice president of strategic marketing at Movellus, noted: "With the constraints being put on modern designs with the chiplet interfaces, the timing constraints are becoming too complicated and too onerous with traditional techniques."

Application-Specific Requirements: Andy Heinig, head of Efficient Electronics at Fraunhofer IIS EAS, observed: "In industrial and automotive, chiplets must be much more robust. That means temperature cycles, mechanical robustness, vibration tests. This is totally different from what we see in data centers."

Improved Manufacturing Economics: The yield improvements from chiplet designs directly translate to lower per-unit costs. A design that achieves 37 percent yield versus 15 percent yield produces more than twice as many functional units per wafer.

Design Flexibility: Chiplets enable mixing and matching of different process nodes. Compute-intensive blocks can use leading-edge nodes while I/O and analog functions use more mature, cost-effective processes.

Faster Time to Market: Reusable chiplet IP blocks can reduce design cycles. Once a chiplet is validated, it can be incorporated into multiple products without redesign.

Customization for Domain-Specific Applications: The modular approach allows chip designers to tailor configurations for specific workloads, from AI inference to automotive safety systems.

Scalability: Chiplet architectures can scale performance by adding more compute chiplets without redesigning the entire system.

Figure 3: Privilege escalation from user to SYSTEM level

Verification Complexity: Ashley Stevens, director of product management and marketing at Arteris, explained the challenge: "If you take a bottom-up approach, if we don't have the other part of the system, then you need very well-defined interfaces, both in hardware and software."

Thermal Management: Power integrity issues compound thermal integrity issues. Heat dissipation becomes more complex when multiple dies are packed into a single package.

Interconnect Overhead: Die-to-die communication adds latency and power consumption compared to on-chip interconnects. The 10 percent area overhead for cross-die communication represents silicon that does not contribute to compute functionality.

Packaging Costs: Advanced packaging technologies required for chiplet integration add cost and complexity. Different applications require different packaging solutions, fragmenting the supply chain.

Lack of Standardization: The absence of universal chiplet interfaces limits the potential for a true plug-and-play marketplace. Each vendor's chiplets may require custom integration work.

Stress and Strain: Physical effects including thermal expansion create mechanical stress on chiplet assemblies. "Not all chiplets are created equal, and not all chiplets behave the same way under stress or in different package configurations," according to Semiconductor Engineering.

A chiplet is an integrated circuit block specifically designed to work with other similar chiplets to form larger, more complex chips. The system is subdivided into functional circuit blocks that are often made of reusable IP blocks.

Packaging Technologies: Chiplets are assembled using advanced packaging techniques including silicon interposers, organic substrates, and bridge technologies. Silicon interposers provide dense interconnects between chiplets but add cost. Organic substrates offer lower cost but with reduced interconnect density. Bridge architectures, such as Intel's EMIB (Embedded Multi-die Interconnect Bridge), provide a middle ground.

Die-to-Die Interconnects: Communication between chiplets requires specialized physical layer (PHY) interfaces. These PHYs must handle high bandwidth with low latency while managing power consumption. Standards like UCIe (Universal Chiplet Interconnect Express) aim to enable interoperability between chiplets from different vendors.

Power Distribution: Each chiplet requires power delivery, and the power distribution network must account for the package-level routing. Early system modeling is essential to ensure power integrity across the multi-die assembly.

Technical context (optional): The reticle limit historically dictated the maximum size of a chip that could be fabricated. Designs exceeding approximately 800 mm² had to be split into multiple dies. As process technologies enabled higher integration, multiple dies were merged into single, more complex integrated circuits. The current chiplet trend represents a reversal driven by economics rather than physical limits.

The chiplet transition affects the entire semiconductor ecosystem, from EDA tool vendors to foundries to system integrators.

EDA Tool Evolution: Design tools must evolve to handle multi-die verification, thermal analysis across package boundaries, and system-level power integrity. Companies including Synopsys, Cadence, and Siemens EDA are developing new capabilities for chiplet design flows.

Foundry Business Models: Foundries may offer chiplet manufacturing services alongside traditional wafer fabrication. The ability to mix process nodes within a single package changes the calculus of which nodes to use for different functions.

Supply Chain Fragmentation: Different chiplets may come from different foundries, creating supply chain complexity. Quality assurance must span multiple manufacturing sources.

Standards Development: Industry consortia are working on chiplet interface standards to enable interoperability. The success of a chiplet marketplace depends on standardization efforts.

Data Center Economics: The cost differential between automotive ($20 per package) and data center ($2,000 per package) chiplets reflects the different performance and reliability requirements. Data center operators must weigh the benefits of chiplet-based designs against the complexity of multi-vendor integration.

Confirmed:

• Chiplet designs improve manufacturing yield compared to equivalent monolithic designs
• Leading-edge process nodes cost significantly more per yielded mm² than mature nodes
• Signal integrity, power integrity, and thermal management are key technical challenges
• Different applications require different packaging solutions and price points
• Major EDA vendors are developing tools for chiplet design flows

Unclear:

• When a true plug-and-play chiplet marketplace will become viable
• Which interconnect standards will achieve widespread adoption
• How quickly third-party chiplets will enter the market at scale
• The long-term reliability of chiplet assemblies under various operating conditions
• Whether chiplet economics will extend to consumer electronics or remain concentrated in data center and automotive applications

Chiplet Summit Outcomes: Industry gatherings continue to shape standards and best practices for chiplet integration.

UCIe Adoption: The Universal Chiplet Interconnect Express standard's adoption rate will indicate whether interoperability is achievable.

Third-Party Chiplet Availability: The emergence of merchant chiplet vendors would signal market maturation.

Packaging Capacity: Advanced packaging capacity at foundries and OSATs (Outsourced Semiconductor Assembly and Test) may become a bottleneck.

Design Tool Capabilities: EDA vendor announcements regarding multi-die design and verification tools will indicate the pace of ecosystem development.

Automotive Qualification: The timeline for chiplet-based designs to achieve automotive-grade qualification will affect adoption in that sector.

1. Semiconductor Engineering - "Chip Architectures Becoming Much More Complex With Chiplets" (January 30, 2025) https://semiengineering.com/chip-architectures-becoming-much-more-complex-with-chiplets/

2. WikiChip - "Chiplet" (Reference documentation) https://en.wikichip.org/wiki/chiplet

3. Intel - "Advanced Packaging" (Vendor documentation) https://www.intel.com/content/www/us/en/newsroom/resources/advanced-packaging.html